Use when writing or reviewing virtual-memory code — x86-64 4/5-level paging, AArch64 VMSAv8-64, RISC-V Sv39/48, PTE flags, TLB invalidation, kernel vs user mappings, large pages, and page-fault debugging. Teaches page-table structure, walk logic, and the TLB-coherency rules that must hold after any PTE change.
